The present invention relates to a process of fabricating a so-called xe2x80x9cvirtual substratexe2x80x9d as well as the virtual substrate and the use thereof in semiconductor devices such as modulation-doped field effect transistors (MODFETs), metal oxide field effect transistors (MOSFETs), strained silicon-based complementary metal oxide semiconductor (CMOS) devices and other devices that require fully-relaxed SiGe layers. The virtual substrate of the present invention contains Si and Ge in a crystalline layer that assumes the bulk lattice constant of a Si1xe2x88x92xGex alloy on either a lattice mismatched Si wafer or silicon-on-insulator (SOI) wafer.
In the semiconductor industry, the Si/S1xe2x88x92xGex heteroepitaxial materials system is of strong interest for future microelectronic applications because the electronic properties of lattice mismatched heterostructures can be tailored for a variety of applications by exploiting band offsets at the interfaces. The most popular application of the Si/Si1xe2x88x92xGex system is heterojunction bipolar transistors (HBTs) that require deposition of a pseudomorphic, i.e., compressively strained so that the in-plane lattice parameter of the layer matches that of the Si substrate, compositionally graded Si1xe2x88x92xGex layer onto the Si substrate. Metal oxide semiconductor field effect transistors (MOSFETs) and modulation-doped field effect transistors (MODFETs) require Si layers under tensile strain to obtain proper conduction band offsets at the interface that enable the formation of a 2D electron gas in the Si quantum well which results in extremely high-electron mobility (on the order of about five-ten times larger than in unstrained Si at room temperature). Si layers under tensile strain are obtained by epitaxial growth on a strain-relaxed Si1xe2x88x92xGex buffer layer (x=0.15-0.35). As mentioned in P. Mooney, Mater. Sci. Eng. R17, 105(1996) and F. Schaeffler, Semiconductor Sci. Tech. 12, 1515 (1997), the strain-relaxed Si1xe2x88x92xGex buffer layer in conjunction with the Si or SOI substrate constitute the so-called xe2x80x9cvirtual substratexe2x80x9d. It is noted that the term xe2x80x9cSiGexe2x80x9d is used sometimes herein to refer to the Si1xe2x88x92xGex layer.
The growth of the strain-relaxed Si1xe2x88x92xGex buffer layer itself is a challenging task since strain relaxation involves controlled nucleation, propagation and interaction of misfit dislocations that terminate with threading arms that extend to the wafer surface and are replicated in any subsequently grown epitaxial layers. These defects are known to have deleterious effects on the properties of electronic and optoelectronic devices. The crystalline quality of the relaxed SiGe layer can be improved by growing compositionally graded buffer layers with thicknesses of up to several micrometers. By using such a technique, the threading dislocation (TD) density in an epitaxial layer grown on top of a buffer layer was reduced from 1010-1011 cmxe2x88x922 for a single uniform composition layer to 106-5xc3x97107 cmxe2x88x922 for a graded composition buffer layer. The major drawback of thick SiGe buffer layers (usually a 1-3 micrometer thickness is necessary to obtain  greater than 95% strain relaxation) is the high-TD density and the inhomogeneous distribution of TDs over the whole wafer surface. Some regions have relatively low TD densities and primarily individual TDs; but other areas contain bundles of TDs as a result of dislocation multiplication which creates dislocation pileups (see, for example, F. K. Legoues, et al., J. Appl. Phys. 71, 4230 (1992) and E. A. Fitzgerald, et al., J. Vac. Sci. and Techn., BIO 1807 (1992)). Moreover, blocking or dipole formation may occur, in some instances, due to dislocation interactions (see E. A. Stach, Phys. Rev. Lett. 84, 947 (2000)).
Surface pits that tend to line up in rows are typically found in the latter areas, thus making these regions of the wafer unusable for many electronic devices. Electronic devices on thick graded Si1xe2x88x92xGex buffer layers also exhibit self-heating effects since SiGe alloys typically have a much lower thermal conductivity than Si. Therefore, devices fabricated on thick SiGe buffer layers are unsuitable for some applications. In addition, the thick graded Si1xe2x88x92xGex buffer layers derived from dislocation pileups have a surface roughness of 10 nm on average, which typically makes such buffer layers unsuitable for device fabrication. For example, it is impossible to use these layers directly for wafer bonding. For that purpose an additional chemical-mechanical polishing (CMP) step is required.
Various strategies have been developed to further reduce the TD density as well as the surface roughness including:
1) The use of an initial low-temperature (LT) buffer layer grown at 450xc2x0 C. and subsequent layer growth at temperatures between 750xc2x0 and 850xc2x0 C. This prior art method makes use of the agglomeration of point defects in the LT-buffer layers that occur at the higher growth temperatures. The agglomerates serve as internal interfaces where dislocations can nucleate and terminate. As a result, the misfit dislocation density that is responsible for the relaxation is maintained, while the TD density is reduced. LT buffer layers can only be grown by molecular beam epitaxy (MBE); this prior art approach cannot be implemented using UHV-CVD.
2) The use of substrate patterning, e.g., etched trenches, to create small mesas, approximately 10-30 micrometers on a side. The trenches serve as sources/sinks for dislocations to nucleate/terminate. When a dislocation terminates at a trench, no TD is formed; however, the misfit segment present at the Si/SiGe interface contributes to strain relaxation. The major drawback with this prior art method is loss of flexibility in device positioning and the loss of usable area. Moreover, it is difficult to obtain high degrees of relaxation ( greater than 80%).
Neither the conventional graded buffer layer methods to achieve strain-relaxed Si1xe2x88x92xGex buffer layers for virtual substrates, nor the alternative approaches to reduce the density of TDs described above provide a solution that fully satisfies the material demands for device applications, i.e., a sufficiently low-TD density, control over the distribution of the TDs and an acceptable surface smoothness.
In some cases, He ion implantation has been employed in forming relaxed SiGe layers. Ion implantation of He into semiconductors is well-known to form bubbles that can be degassed and enlarged (Ostwald ripening) during subsequent annealing (see, for example, H. Trinkaus, et al., Appl. Phys. Lett. 76, 3552 (2000), and D. M. Follstaedt, et al., Appl. Phys. Lett. 69, 2059 (1996)). The bubbles have been evaluated for uses such as gettering metallic impurities or altering electronic properties of semiconductors. Moreover, the bubbles have also been evaluated as sources for heterogeneous dislocation nucleation.
It has also been shown that the binding energy between bubbles and dislocations is quite large (about 600 eV for a 10 ni radius of the bubble) and that the interaction of He bubbles with dislocations significantly alters the misfit dislocation pattern. It consists of very short ( less than 50 nm) misfit dislocation segments rather than the longer ( greater than 1 xcexcm) ones that occur in graded buffer layer growth. The interaction of He bubbles with dislocations also significantly changes the relaxation behavior of strained Si1xe2x88x92xGex layers. Moreover, the degree of relaxation is greater compared to an unimplanted control sample when the same heat treatment is applied to both samples. To achieve significant strain relaxation, a dose of 2xc3x971016 cmxe2x88x922 He implanted about 80 nm below the Si/SiGe interface is required (M. Luysberg, D. Kirch, H. Trinkaus, B. Hollaender, S. Lenk, S. Mantl, H. J. Herzog, T. Hackbarth, P. F. Fichtner, Microscopy on Serniconducting Materials, IOP publishing, Oxford 2001, to be published). Although the strain relaxation mechanism is very different from that which occurs in graded buffer layers, the TD density remains unsatisfactorily large ( greater than 107 cmxe2x88x922 at best for Si0.80Ge0.20). Lower TD densities are obtained only when little strain relaxation occurs.
In view of the drawbacks mentioned-above with prior art approaches for fabricating strain-relaxed Si1xe2x88x92xGex buffer layers on Si substrates as well as on silicon-on-insulator substrates (SOI), there exists a need to develop a new and improved process which is capable of fabricating strain-relaxed Si1xe2x88x92xGex buffer layers on Si or silicon-on-insulator (SOI) substrates having a reduced TD density, a homogeneous distribution of misfit dislocations and a remarkably low surface smoothness.
One aspect of the present invention relates to a process of fabricating a relaxed Si1xe2x88x92xGex buffer layer having a low-density of TDs on a single crystalline surface. Broadly, the inventive process, which forms a so-called xe2x80x98virtual substratexe2x80x99 comprises the steps of: depositing a strictly pseudomorphic epitaxial layer of Si1xe2x88x92xGex (i.e., a layer that is completely free of dislocations) on a single crystalline surface of a substrate; ion implanting atoms of a light element such as He into the substrate; and annealing the substrate at a temperature above 650xc2x0 C.
Even though He implantation is known, applicants have determined optimum processing conditions for implanting He ions below the Si/Si1xe2x88x92xGex interface and subsequent thermal annealing that yield a quite different relaxation mechanism resulting in a reduced threading dislocation density (e.g., 104-106 cmxe2x88x922 for Si0.15Ge0.85) of a thin ( less than 300 nm) SiGe layer.
It is of key importance for successful device performance that the strain-relaxed single crystal Si1xe2x88x92xGex layer contains as few defects, which are primarily threading dislocations (TDs), as possible; the upper limit that can be tolerated for TDs mentioned in recent publications is 106 cmxe2x88x922. Using the inventive process, it is possible to obtain relaxed Si1xe2x88x92xGex layers having TD densities below this limit, in contrast to the commonly used state-of-the-art linearly- or step-graded buffer layers that typically have TDs in the range between 1xc3x97106 to 5xc3x97107 cmxe2x88x922 on 8xe2x80x3 wafers at alloy compositions as high as Si0.8Ge0.2.
Another aspect of the present invention relates to a virtual substrate that is formed using the inventive process. Specifically, the inventive virtual substrate comprises
a substrate; and
a partially relaxed single crystalline Si1xe2x88x92xGex layer atop the substrate, wherein the partially relaxed single crystalline Si1xe2x88x92xGex layer has a thickness of less than about 300 nm, a threading dislocation density of less than 106 cmxe2x88x922, and significant relaxation of greater than 30%.
In some embodiments of the present invention, the epitaxial Si1xe2x88x92xGex layer includes C having a concentration of from about 1xc3x971019 to about 2xc3x971021 cmxe2x88x923 therein.
A still further aspect of the present invention relates to semiconductor structures that are formed using the processing steps of the present invention. Broadly, the inventive semiconductor structure comprises:
a substrate;
a first single crystalline layer atop said substrate;
a second highly defective single crystalline layer atop said first single crystalline layer, said second highly defective single crystalline layer comprising planar defects which serve as sources and sinks of dislocation loops;
a third single crystalline layer of essentially the same composition as the first single crystalline layer, said third single crystalline layer comprising threading dislocations terminating at the interface formed between the third and fourth layers; and
a fourth relaxed single crystalline layer having a lattice parameter different from said third layer formed atop said third layer.